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PL 3120/PL 3150/PL 3170 Power Line Smart Transceiver Data Book 167
The performance of this power supply is somewhat sensitive to layout. Minimizing the length of the net from the
Drain of the VIPer20A IC is of particular importance in controlling conducted emissions. In order to reduce the time
required to successfully implement this supply, a recommended layout is provided below.
Figure 5.8 Recommended Layout of the Pre-Verified Isolated Switching Supply
While each new product must be verified for regulatory compliance and communication performance, using this
supply simplifies the development task since an instance of this design has been pre-verified. This supply was tested
in combination with PL 3120 Smart Transceiver reference design #1217 from Appendix A and the isolated Line-to-
Neutral coupling circuit Example 2 from Chapter 4. This combination passed EN50065-1 and FCC regulations for
conducted emissions with 8dB of margin when the output of the supply was floating (not connected to earth ground).
In applications requiring a grounded output, adding the optional common mode choke provides a passing result. This
supply and PL reference design was also verified to pass all of the communication performance tests of Chapter 7. In
addition, this supply and coupling circuit combination passed the surge tests documented for the Example 2 coupling
circuit in Table 4.14 in Chapter 4.
- /PL 3150 1
- /PL 3170 1
- Table of Contents 3
- Product Overview 9
- LONWORKS Networks 9
- Three Product Families 10
- Power Line Signaling 10
- Restricted 11
- Forward Error Correction 12
- Powerful Output Amplifier 12
- Wide Dynamic Range 12
- Low Current Consumption 12
- Restrictions Under 13
- Consideration 13
- Overview 17
- Table 2.5 ALU Instructions 22
- Memory Allocation Overview 23
- • Unique 48-bit Neuron ID 24
- Static RAM 26
- Pre-programmed ROM 26
- Input/Output 27
- Clock Input 28
- PL Smart 29
- Transceiver 29
- Connections 30
- TXON Output Signal 30
- Additional Functions 31
- RESET~ Pin 32
- Reset Processes and Timing 34
- SERVICE~ Pin 39
- Signal Out 40
- Integrity Mechanisms 41
- Reset Processing 43
- Signatures 43
- Hardware Considerations 46
- Pulsecount Input 50
- I/O Timing Issues 51
- Direct I/O Objects 53
- Byte Input/Output 55
- Leveldetect Input 56
- Nibble Input/Output 57
- Parallel I/O Objects 58
- Parallel Input/Output 60
- Serial I/O Objects 66
- C Input/Output 68
- Magcard Input 70
- Magtrack1 Input 72
- Magcard Bitstream Input 73
- Serial Input/Output 77
- Touch Input/Output 79
- Wiegand Input 81
- SCI (UART) Input/Output 82
- SPI Input/Output 83
- IO_7 input bit io_p7_in; 84
- 1 = clockedge(+) 85
- 0 = clockedge(-) 85
- 1 = [default] 85
- 0 = invert 85
- SPI Master 87
- SPI Master (Neurowire 87
- SPI Slave 88
- Timer/Counter Input Objects 89
- Dualslope Input 90
- Edgelog Input 91
- Infrared Input 93
- Ontime Input 94
- Period Input 94
- Reference Figure 3.40 95
- Quadrature Input 97
- Return from function 88 µs 98
- Totalcount Input 99
- Timer/Counter Output Objects 100
- Frequency Output 102
- Infrared Pattern Output 103
- Oneshot Output 104
- Pulsecount Output 105
- Pulsewidth Output 106
- Triac Output 107
- Triggered Count Output 109
- (Clock Select + n) 110
- Clock Select 111
- Introduction 113
- IllinoisCap/154MKP275KB 116
- IllinoisCap/683MKP275KB 120
- IllinoisCap/224MKP275KB 128
- Table 4.12 136
- Coupling Circuit Tutorial 137
- Power Line Coupling Basics 139
- Power Line Coupling Details 141
- Safety Issues 146
- Ground Leakage Currents 148
- 3-Phase Coupling Circuits 149
- Line Surge Protection 155
- Transmission 164
- Retransmit 164
- Power Supply 166
- PL 3120/ PL 3170 167
- Reference Design 167
- (See Appendix A) 167
- 12.6 VAC @100 mA 168
- (See Text) 172
- Optional 172
- Quasi-peak detector 181
- Average detector 181
- Frequency (Hz) 186
- Attenuation (dB) 186
- Conducted Emissions Testing 194
- EMI Remedies 195
- Verification Procedure 201
- Power Line Test Isolator 202
- Test Equipment 202
- 30.1k Ω ±1%, 1/4W 204
- Good Citizen Verification 205
- ISOLATOR 207
- Checks 213
- Dual Carrier Frequency Mode 215
- CENELEC Access Protocol 215
- Power Management 216
- Standard Transceiver Types 217
- Development Tools Support 218
- ShortStack Developer’s Kit 220
- Reference Design Files 225
- (DSK) Reference Designs 227
- Device Checklist 232
- Ω @100kHz 234
- Schematic 239
- Production Test Guidelines 243
- A/D, D/A- based Test System 245
- Test System Verification 247
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